Signal switches and in particular MOS-switches are used in many circuits, such as track and holds, programmable gain amplifiers (PGA), tunable filters or switched capacitor applications. When designing switched capacitor circuits on a low voltage supply there is a difficulty of implementing the signal or MOS-switches. Typically, in a switched capacitor circuit, an analog input signal Vi is sampled through a MOS-switch or transmission gate as shown in FIG. 1. Ideally, the switch in the on-stateacts as a fixed linear conductance gds. In practice the conductance of the switch varies with the signal voltage as shown in FIG. 1. Plotted in FIG. 1 is the switch conductance versus the input signal Vi for three different supply voltages Vdd. The dashed line shows the individual conductances of the NMOS and PMOS devices and the solid line shows the effective parallel conductance.
In the first case Vdd is much larger than the sum of two threshold voltages Vtn and Vtp. In this case, it is easy to achieve a large on conductance from rail to rail for the input signal Vi.
In the second case the supply voltage Vdd is comparable to the sum of the threshold voltages and there is a substantial drop in conductance when the input signal Vi approaches Vdd/2.
In the third case, where the supply voltage Vdd is less than the sum of the two threshold voltages, there is a large range of the input signal VI for which the switch will not conduct.
To overcome this problem it was suggested by Fujimoro, L. Longo, A. Hirapethian, et al. “In 90-DBSNR 2.5 MHz output rate ADC using cascaded multi-bit delta sigma modulation at 8× oversampling rate”, JSSC, vol. 35, December 2000 to use low threshold voltages devices for switches in the signal path. To achieve this additional masks for processing those switches are necessary and the manufacturing process becomes much more complex.
Therefore it was proposed to use a charge pump and to increase the supply voltage for the switch drivers locally. This was suggested by A. R. Feldmann “A 13 bit, 1.4 Ms/s sigma delta modulator for RF baseband channel application”, JSSC, vol. 83, October 1998. In this approach the gate overdrive is signal dependent leading to non linearities and harmonic distortion of the applied analog signal.
Conventional implementations result in voltage stress that exceeds the supply by a large margin.
Another approach to overcome the above mentioned problem is to keep the gate overdrive of the MOS-switch constant by employing a technique called boot-strapping. In A. M. Abo, P. R. Gray “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipe-line Analog-to-Digital Converter”, IEEE journal of solid-state circuits vol. 34, no. 5, may 1999, a boot-strap circuit and switching device is described.
FIG. 2 shows a bootstrap MOS-switch according to the state of the art. Transmission gates are used extensively in switch-capacitor gate stages of a pipeline. Since the threshold voltages of the NMOS and PMOS transistors are 0.7V and 0.9V, respectively, conventional transmission gates with any usable signal swing are not directly realizable. Therefore a bootstrap switch as shown in FIG. 2 was suggested. Consequently a boot-stapped switch was designed to observe device reliability considerations. The switch shown in FIG. 2 according to the state of the art is conceptually a single NMOS transistor. In the “off”-state the gate is grounded and the device is cut off. In the “on”-state a constant voltage of Vdd is supplied across the gate-to-source terminals, and a low on-resistance is established from drain to source independent of the input signal. Although the absolute voltage applied to the gate may exceed the supply voltage Vdd for a positive input signal, none of the terminal-to-terminal device voltages exceeds Vdd.
FIG. 3 shows a bootstrap circuit according to prior art. The bootstrap circuit shown in FIG. 3 operates on a single phase clock φ that turns the switch M11 on and off. During the off phase φ is low. Devices M7 and M10 discharge the gate of M11 to ground. At the same time, the supply voltage Vdd is supplied across capacitor C3 by MOS-FET M3 and MOS-FET M12. The capacitor C3 acts as a battery across the gate and source during the “on” phase. MOS-FET M8 and MOS-FET M9 isolate the switch from capacitor C3 while it is charged. When the phase clock φ goes high, the MOS-FET M5 pulls down the gate of MOS-FET M8, allowing charge from the battery capacitor C3 to flow onto gate G of the switch M11. The MOS-FET M9 enables the gate G to track the input voltage S shifted by Vdd, keeping the gates source voltage Vgs constant regardless of the input signal. For instance, when the source S is at Vdd, then the gate G is at 2×Vdd, however, the gate source voltage Vgs is as high as the supply voltage Vdd. Because the body (N-well) of MOS-FET M8 is tied to is source, latch up is suppressed. The capacitor C3 must be efficiently large to supply charge to the gate G of the switching device in addition to all parasitic capacitance in the charging path.
The disadvantage of the bootstrap circuit and switching device according to the state of the art as shown in FIG. 3 resides in that a clock signal φ is necessary to recharge the battery capacitor C3. The boot-strap circuit of FIG. 3 needs a clock signal and cannot be used for continues time switches for instance in PGAs or tunable filters.